10-bits current-mode Successive Approximation Analog-to-Digital Converter
(CMOS 130 nm technology)

Expected data rate: 1 Mbit/s

Chip area: 0.01 mm^2 (probably the smallest area among such converters in the world)

No. of transistors: ca. 1000

A flexible system with a programmable number of bits at the output of the ADC. Power consumption automatically adjusts to the number of bits. With a smaller number of bits achievable speed is relatively larger.

Target applications:

• Low power medical diagnostics systems based on Wireless Body Area Networks (WBAN),
• Low power analog artificial neural networks implemented in hardware,
• Analog Front End (AFE) ASIC used in nuclear medicine,
• Applications that require the use of dozens of such converters in a single chip (hence the low area is a critical parameter).

Author: Rafal Dlugosz (University of Technology and Life Sciences, Bydgoszcz Poland) in the cooperation with the IHP Microelectronics Institute, Frankfurt (Oder), Germany